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copyright ? 201 5 future technology devices international limited 1 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 future technology devices international ltd . ft 42 22 h ( usb 2.0 to quad spi / i 2 c bridge ic ) ft4222 h is a usb2.0 to quad - spi/ i 2 c in terface device controller with the following advanced features: ? single chip usb2.0 hi - speed to spi / i 2 c bridge with a variety of configurations ? entire usb protocol handled on the chip . ? on - chip otp memory for usb vendor id (vid), product id (pid), device s erial number, product description string and various other vender specific data. ? configurabl e industry standard spi master/slave interface controller ? support configurable data width with single, dual, quad data width transfer mode in spi master ? sck can sup port up to 30mhz in spi master ? up to 2 8 mbps data transfer rate in spi master with quad mode transfer ? support single bit data transfer with full - duplex transfer in spi slave ? support up to 4 channels slave selection control pins in spi master application ? con figurable i 2 c master/slave interface controller conform ing to i 2 c v2.1 and v3.0 specification . ? support 4 speed modes defined in i 2 c - bus specification , standard mode (sm) up to 100 k bit/s , fast mode (fm) up to 400 k bit/s , fast mode plus (fm+) up to 1mbit/s , and high speed mode (hs) up to 3.4 mbit/s ? configurable gpios can be easily controlled by software applications via usb bus ? u sb battery charger detection. ? device supplied pre - programmed with unique usb serial number . ? usb power configurations; supports bus - powered, self - powered and bus - powered with power switching . ? +5v usb vbus detection engine ? integrated 5v - 3.3v - 1.8v level conve rter for usb i/o . ? true 3.3v cmos drive output and ttl input. (operates down to 1v8 with external pull - ups) ? configurable i /o pin output drive strength ; 4 ma(min) and 16 ma(max) ? integrated power - on - reset circuit. ? usb2.0 low operating and suspend current ; 68 ma (active - typ) and 375 a (suspend - typ) . ? uhci / ohci / ehci / xhci host controller compati ble . ? ftdis royalty ? e xtended operating temperature range ; - 40 to 85 ? ? available in compac t pb - free 32 pin v qf n packages ( rohs compliant) . neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or re produced in any material or electronic form without the p rior written consent of the copyright holder. this product and its documentation are supplied on an as - is basis and no warranty as to their suitability for any particular purpose is either made or implied. future technology devices international ltd will n ot accept any claim for damages howsoever arising as a result of use or failure of this product. your statutory rights are not affected. this product or any variant of it is not intended for use in any medical appliance, device or system in which the failu re of the product might reasonably be expected to result in personal injury. this document provides preliminary information that may be subject to change without notice. no freedom to use patents or other intellectual property rights is implied by the publ ication of this document. future technology devices international ltd, unit 1, 2 seaward place, centurion business park , glasgow g41 1hh united kingdom. scotland registered company number: sc136640
copyright ? 201 5 future technology devices international limited 2 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 1 typical applications ? usb to single mode spi master contro ller ? usb to dual mode spi master controller ? usb to quad mode spi master controller ? usb to single spi slave controller ? usb to i 2 c master interface controller ? usb to i 2 c slave interface controller ? utilising usb to add system modularity ? incorporate usb inter face to enable pc transfers for development system communication ? usb industrial control ? usb data ac quisition ? accessory connectivity solutions for mobiles and tablets ? usb dongle implementations for software / hardware encryption and wireless modules ? detect usb dedicated charging ports, to allow for high current battery charging in portable devices. 1.1 driver support royalty free d2xx direct drivers (usb drivers + dll s/w interface) ? windows 10 32, 64 - bit ? windows 8.1 32, 64 - bit ? windows 8 32, 64 - bit ? windows 7 32, 64 - bit ? server 200 8 r2 ? server 2012 r2 for driver installation, please refer to http://www.ftdichip.com/documents/installguides.htm 1.2 part numbers part number package ft 42 22 h q - x 32 pi n v qfn note: packing codes for x is: - r : taped and reel , 5 ,000pcs per reel - t : tray packing , 490pcs per tray for example: ft 42 22 h q - r is 5 ,000pcs taped and reel packing
copyright ? 201 5 future technology devices international limited 3 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 1.3 usb compliant the ft 4 22 2h is fully compliant with the usb 2.0 specification and has been given the usb - if test - id (tid) 40 001 59 9 .
copyright ? 201 5 future technology devices international limited 4 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 2 ft 42 22 h block diagram figure 2 . 1 ft 42 22 h block diagram for a description of each function please refer to section 4.
copyright ? 201 5 future technology devices international limited 5 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 table of contents 1 typical applications ................................ ................................ ...... 2 1.1 driver support ................................ ................................ .................... 2 1.2 part numbers ................................ ................................ ...................... 2 1.3 usb compliant ................................ ................................ .................... 3 2 ft 42 22 h block diagram ................................ ............................... 4 3 device pin out and signal description ................................ .......... 7 3.1 vqfn - 32 package pin out ................................ ................................ ... 7 3.2 pin description ................................ ................................ ................... 8 4 function descriptio n ................................ ................................ ... 10 4.1 key features ................................ ................................ ..................... 10 4.2 functional block descriptions ................................ ........................... 11 5 ft 4 222h chip mode configuration and spi/ i 2 c interface .......... 14 5.1 chip mode configuration ................................ ................................ ... 14 5.2 spi bus interface ................................ ................................ ............. 15 5.2.1 spi pin definition ................................ ................................ ................................ ....... 15 5.2.2 spi bus protocol ................................ ................................ ................................ ........ 15 5.2.3 sck format ................................ ................................ ................................ .............. 17 5.2.4 spi timing ................................ ................................ ................................ ................ 18 5.3 i 2 c bus interface ................................ ................................ .............. 20 5.3.1 i 2 c pin definition ................................ ................................ ................................ ....... 20 5.3.2 i 2 c bus protocol ................................ ................................ ................................ ......... 20 5.3.3 i 2 c slave address ................................ ................................ ................................ ...... 21 5.3.4 i 2 c timing ................................ ................................ ................................ ................ 21 5.4 gpios ................................ ................................ ............................... 23 6 devices characteristics and ratings ................................ ........... 24 6.1 absolute m aximum ratings ................................ ............................... 24 6.2 esd and latch - up specifications ................................ ....................... 24 6.3 dc characteristics ................................ ................................ ............. 25 6.4 o tp memory reliability characteristics ................................ ............ 30 7 FT4222H configurations ................................ ............................. 31 7.1 usb bus powered configuration ................................ ...................... 31 7.2 self powered configuration with 5v source input ............................ 32 7.3 self powered configuration with 3.3v source in .............................. 33 7.4 crystal oscillator configuration ................................ ........................ 34 7.5 usb battery charging detection ................................ ....................... 35 8 applicatio n examples ................................ ................................ . 36
copyright ? 201 5 future technology devices international limited 6 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 9 internal o tp memory configuration ................................ ........... 38 9.1 default values ................................ ................................ .................. 38 9.2 method of programming the o tp memory ................................ ......... 41 9.2.1 programming the otp memory over usb ................................ ................................ ...... 41 10 package parameters ................................ ................................ ... 42 10.1 v qfn - 32 package mechanical dimensions ................................ ..... 42 10.2 v qfn - 32 package markings ................................ ........................... 43 10.3 solder reflow profile ................................ ................................ ..... 44 11 contact information ................................ ................................ ... 45 appendix a C references ................................ ................................ ........... 46 appendix b - list of figures and tables ................................ ..................... 47 appendix c - revision history ................................ ................................ .... 49
copyright ? 201 5 future technology devices international limited 7 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 3 device pin out and signal description 3.1 v qfn - 32 package pin out figure 3 . 1 pin configuration v qfn - 3 2 (top - down view)
copyright ? 201 5 future technology devices international limited 8 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 3.2 pin description FT4222H pin no. pin name type description 1 debugger i/o debugging pin. sh ould be reserved and tied to high 2 stest_rstn i chip reset input for test mode . active low. should be reserved and tied to high. 3 resetn i chip reset input for non - test mode operation . a ctive low . 4 dcnf0 i chip mode configuration selection bit 0 . refer to section 5.1 5 dcnf1 i chip mode configuration selection bit 1 . refer t o section 5.1 6 dgnd p digital groun d 7 vccio ** p +3.3v /2.5v/1.8v supply voltage. this is the supply voltage for all the i/o ports. this pin shall be connected to pin 25 when i/o ports are working at 3.3v 8 sck i/o spi interface clock. serial clock output for spi master; serial clock inpu t for spi slave mode 9 miso i/o in spi master single mode, it is master serial data input. in spi ma s ter dual/quad mode, it i s spi data bus bit 1. in spi slave mode, it is slave serial data output. 10 mo si i/o in spi master single mode, it is master serial data output. in spi ma s ter dual/quad mode, it i s spi d ata bus bit 0 . in spi slave mode, it is slave serial data input. 11 io2 i/o quad spi data bus bit 2 12 io3 i/o quad spi data bus bit 3 13 gpio0/ss1o/scl i/o gpio 0 (default) can be confi gured as slave selection 1 , output pin for spi master mode or serial clock for i 2 c mode 14 gpio1/ss2o/sda i/o gpio 1 (default) can be configured as slave selection 2 , output pin for spi master mode or serial data for i 2 c mode 15 gpio2/ss3o/susp_out i/o g pio 2 (default) can be configured as slave selection 3 , output pin for spi master mode or usb suspend output indicator 16 gpio3/wakeup/intr i/o gpio 3 (default) and can be configured as usb remote wakeup input pin or interrupt input 17 ss0o o s lave selec tion 0 , output pin for spi master mode . 18 xsci ai crystal oscillator input , 12m h z only. related application circuit can be referred to in section7.4 19 xsco ao cryst al oscillator output, 12m h z only. related application
copyright ? 201 5 future technology devices international limited 9 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 FT4222H pin no. pin name type description circuit can be referred to in sec tion7.4 20 ugnd p usb analog ground 21 rref ai usb peripheral reference voltage input. connect 12kohm +/ - 1% resistor to gnd. 22 dm ai/o usb peripheral bidirectional dm line. 23 dp ai/o usb peripheral bidirectional dp line. 24 ugnd p usb analog ground 25 vout3v3 ** p +3.3v voltag e out may be used to power vccio . when vccin is supplied with 3.3v, this pin is a power input pin. connect to pin 26. 26 vcc in ** p + 5.0 v (or 3.3v) supply voltag e in power source - in to embedded regulator. 27 agnd p analog gr ound 28 dgnd p digital ground 29 vpp p + 6.5v supply voltag e in power source for programming embedded otp . it s hould be kept floating or 0v when not in programming mode 30 vbus_det i vbus d etection input. it i s a +5.0v toler a n t pin 31 bcd_det o batte ry c harger d etect ion i ndicat or out put when the device is connected to a dedicated battery charger port. polarity can be defined 32 ss i spi slave selection indicator from spi master. this pin is active in spi slave mode . it must be tied to high when spi m aster mode enable d . table 3 . 1 FT4222H pin description * *if vccin is supplied with 3.3v power input, then vout3v3 and vccio must also be driven with this 3.3v power source
copyright ? 201 5 future technology devices international limited 10 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 4 function description the FT4222H is a hi - speed usb2.0 - to - quad spi/ i 2 c device controller in a compact 32 - pin v qfn package. the FT4222H requires an external crystal ( 12 mhz ) for the internal pll to operate. it supports multi - voltage io, 3.3v, 2.5v or 1.8v. it also provides 128 bytes one - time - programmable (otp) memory space for storing vendor specific information. t h e FT4222H contains spi/ i 2 c configurable interfaces. the spi interface can be configured in master mode with single, dual, or quad bits data width transfer or in slave mode with single bit data width transfer. the i 2 c interface can be configured in master or slave mode. 4.1 key features functional integration. the ft42 2 2h is a usb 2.0 hi - speed (480mbits/s) to flexible and configurable spi or i 2 c interfaces ic . the ft42 2 2h includ es an integrated +1.8v and +3.3v low drop - out (ldo) regulator and 12mhz to 480mhz pll. it also includes power - on - reset (por), vbus detec tion with 5v - tolerance and 128 b ytes one - time - programmable( otp ) memory which simplify external circui t design and reduce external component count. usb 2.0 hi - speed device controller . the ft42 22h integrates a usb protocol engine which controls the physical universal transceiver macrocell interface (utmi) and handles all aspects of the usb 2.0 hi - speed interface. it contains one control endpoint, and 4 - pairs of in and out endpoints. these endpoints can implement up to 4 indepe nde nt interfaces/applications mapped to combined i 2 c , gpio, spi interface s . highly i ntegrated usb 2.0 to c onfigurable spi bridge . the ft42 22h provide s th e bridge function between a usb2.0 device , upstream port and an spi mas ter/slave. a support library , lib ft4222 , based on ftdi s d2xx driver, enables easy configur ation of the spi as a master or slave . o perating clock frequency on the spi bus, clock phase and polarity, transfer data bit width mode, and the n umber of slave selection controls are also configurable . the max imum spi interface operating clock can be set up to 4 0mhz in master mode and 20mhz in slave mode. with quad mode ( 4 - bits) data bus width, the max data transfer throughput can be up to 28 mbps. usb to c onfigurable i 2 c controller . the FT4222H also provides the bridge function between a usb2.0 device upstream port and an i 2 c mast er/slave interface. a support library , lib ft4222 , based on ftdi s d2xx driver, enables easy configuration of the i 2 c as either a master or slave , including t arget operating speed and bus protocol on the i 2 c bus. the device can run at c o mmon i 2 c bus speeds , standard mode (sm), fast mode (fm), fast mode plus (fm+), and high speed mode (hs ). a higher bit rate on the i 2 c bus is also configurable up to 6.66mbit/s. clock stretching is supported to conform to v2.1 and v3.0 of the i 2 c specification. configurable gpios . there are 4 gpio pins in the ft42 22h that can be configured for differen t purpose s , such as a suspend indicator output , remote wake up input , an interrupt input or gen e ral purpose input/output . the se gpio s can be easily initialized and fully controlled at the usb host side by the applica tion programming interface ( api ) defined in lib ft4222 . s ignal driv e strength and slew rate of these gpios can be configured via the ft_prog utility for different design needs . embedded otp memory. the internal o tp memory in the ft 4222h is used to s tore usb vendor id (vid), product id (pid), device serial number, product description string and various other usb configuration descriptors. with this embedded otp memory, the device can store vendor specific information and save the cost on bom . the des criptors can be programmed using the ftdi utility software called ft_prog , which can be downloaded from the ftdi utilities page on the ftdi website ( http://www.ftdichip.com/support/utilities.htm#ft_prog ). power management . usb 2.0 suspend/resume and remote wakeup are fully supported. the phy will be put to a power saving mode and the clock to most of the digital circuits will be stopped when the device is suspended. source power and power consumption. the ft 4 22 2h is capable of operating at a voltage supply of + 3.3 v or +5 . 0 v with a nominal operational mode current of 68 ma and a nominal usb suspend mode current of 375 a. this allows greater margin for peripheral designs to meet the usb suspend mode current limit of 2.5ma . an integrated level converter within the ft 4222 h allows the device to interface with log ic running at +1.8v, 2.5v or +3.3v. (note: external pull - ups are recommended for io <3v3).
copyright ? 201 5 future technology devices international limited 11 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 4.2 functional block descriptions the following paragraphs detail each function within the ft 42 22 h . please refer to the block diagram shown in figure 2 . 1 usb2.0 utmi phy . the universal transceiver macrocell interfac e (utmi) is a physical interface cell. this block handles the f ull speed and h igh s peed serdes (serialise - deserialise) function for the usb tx/rx data. it also provides the clocks for the rest of the chip. a 12 mhz crystal should be connected to the x s ci and x sco pins. a 12 k ohm resistor should be connected between ref and gnd on the pcb. the utmi phy functions include: ? supports 480 mbit/s "hi - speed" (hs) and 12 mbit/s full speed (fs). ? sync/eop generation and checking. ? data and clock recovery from a serial stream on the usb. ? bit - stuffing/unstuffing; bit stuff error detection. ? manages usb resume, wake up and suspend functions. single parallel data clock output with on - chip pll to generate higher speed serial data clocks usb device controller . the usb d evice controller in the FT4222H controls and manages the interface between the utmi phy and the interface s of the chip. it provid es 9 endpoints to fit into the FT4222H applications. the usb device controller function includes : ? endpoint - 0 for a control pi pe with max packet size 64 bytes ? 4 endpoints for bulk - in pipe with configurable max packet size up to 512 bytes ? 4 endpoints for bulk - out pipe with configurable max packet size up to 512 bytes ? multiple interfaces configuration support ? s uspend detection and power management ? r emote wake - up support ? f ully compatible to usb2.0 specification requirement endpoint buffer . for fulfilling the max packet size requirement and high performance da ta transfer throughput, the endpoint buffer is 4160 bytes sram with configur able size management to each endpoint. it can be configured as single or double buffers and adjustable size for each endpoint. q uad spi master/slave controller. t he q uad spi is a fully configurable spi master/slave device, which allows the user to configu re polarity and phase of the serial clock signal s ck. when spi is configured as a master, it can be configured automatically to drive slave select outputs (ss 3 o C ss0o), and address the spi slave device to exchange serially shifted data. the data bus can b e configured as single ( 1bit), dual ( 2 - bits) and quad ( 4 - bits) mode for different transfer request s and application s . the interface operating clock can be easily configured up to 3 0mhz. when spi is configured as a slave, the spi engine can support one slav e port and operate a single data mode transfer. the max acceptable operating clock can be up to 20mhz. the q uad spi controller can be configured via a support library, lib ft4222 . for d etails refer to the user guide for libft4222 . q uad spi as master functions include: ? single mode (1 - bit) data transfer with full duplex serial data transfer ? dual mode (2 - bit ) data transfer ? quad mode (4 - bit ) data trans fer ? up to 4 spi slave channels can be addressed via pins ss3o~ss0o ? shared data bus to minimize related pin count s ? 4 types of transfer format can be selected by phase and polarity ? configurab le interface clock on sck as 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/1 28 , 1/256 of 80 mhz , 60 mhz ,48mhz and 24 mhz
copyright ? 201 5 future technology devices international limited 12 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 sck freq. ( hz) sck = operating clock * the following ratio operating clock max throughput can be expected 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 80mhz 28 .1 mbps * 40m * 20m * 10m 5m 2.5m 1.25m 625k 312.5k 60mhz 20. 5mbps * 30m * 15m 7.5m 3.75m 1.875m 937.5k 468.75k 234.375k 48mhz 16.3mbps* 24m * 12m 6m 3m 1.5m 750k 375k 187.5k 24 mhz 8 . 0 mbps * 12 m * 6 m 3 m 1.5 m 750k 375 k 187.5 k 93 . 7 5k table 4 . 1 sck operating frequency in sp i master mode *the max . throughput can be expected under the cond i tion of quad mode transfer s with a high operating frequency on sck. it a ls o depends on the usb bus transfer condition. for example, the max throughput that can be expected is up to 28 .1mbps when the op erating clock is equal to 80mhz, sck is set as 20mhz or 40mhz , the data bus is operating in quad mode and the usb bus is operating at hi - speed usb rates with sufficient bandwidth. q uad spi as slave functions include: ? single mode (1 - bit) data transfer with full duplex serial data transfer ? can accept sck operating frequency up to 20 mhz operating clock frequency max acceptable frequency on sck 80mhz <= 20mhz 60mhz <= 15mhz 48mhz <= 12mhz 24 mhz <= 6 mhz table 4 . 2 max. acceptable operating frequency on sck in spi slave mode i 2 c master/slave controller. i 2 c (inter integrated circuit) is a multi - master serial bus invented by philips. i 2 c uses two bi - directional open - drain wires called se rial data (sda) a nd serial clock (scl). common i 2 c bus speeds are the standard mode (sm) with bit rate up to 100 k bit/s , fast mode (fm) with the bit rate up to 400 kbit/s , fast mode plus (fm+) with the bit rate up to 1 mbit/s , and high speed mode (hs) with the bit rate up to 3.4 mbit/s . r efer to the i 2 c specification for more information on the protocol. the ft 422 2 h device can operates as master or slave, and the ma jor functions include: ? m aster or slave mode configurable ? f ully compatible to v2.1 and v3 specification ? 7 - bit address support ? support 4 speed configurations defined in i 2 c - bus specification ? support bit rate up to 6.66mbit/s both in master and slave mode ? clock stre t ching support in master and slave mode gpios . FT4222H contains 4 gpio pins for various functions. the driv e strength, slew rate control and pull high/low resistors can be con figured in the vend o r configur able area of the otp via ft_prog. when the usb gpio interface is enable d and support ed , gpios can be directly controlled by ap is ( application programming interface) which are defined in the support library, lib ft4222 , to match the requirement. gpios in the FT4222H functions include: ? gpio0 can be configured as gpio0 or i 2 c scl or spim slave selection ss1o ? gpio1 can be configured a s gpio1 or i 2 c sda or spim slave selection ss2o
copyright ? 201 5 future technology devices international limited 13 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 ? gpio2 can be configured as gpio2 or usb suspend status output(susp) or spim slave selection ss3o ? gpio3 can be configured as gpio3 or usb remote wake - up input(wake) or external interrupt input(intr) ? a djustable d riving strength : 4ma/8ma/12ma/16ma ? slew rate, pull high/low resistor, open drain configurable ? wake can be configured as rising or falling edge trigger ed ? susp trigger mode can be configured as rising edge , falling edge, high level and low level trigger f or c onfiguration d etails refer to section 9.1 . buil t - in clock synthesizer . w ith an on - chip clock synthesizer, the FT4222H may operate with a low - cost 12 mhz crystal (or oscillator) by connecting to x sci and x sc o, and generates a standard internal 480 mhz clock for the usb interface. t he clock synthesi zer takes t he 480mhz clock from the embedded utmi phy and generates the 80mhz, 60mhz , 48mhz and 24 mhz as reference clock s . the u ser can select one of these reference clocks via the api, ft4222_setclock which is defined in lib ft4222 , as the system operating clock. the system operating clock will be the base and u sed by the embedded functions to generate the required interface clock . protocol control engine . the FT4222H has an embedded and robust contro l engine . it deal s with the usb enumeration commands and flow control between driver and function such as spi or i 2 c devices. it can perform the bridge function initialization and enable an exceptional data transfer performance through the usb bus. it collects and summarizes the spi and i 2 c bus protocol and simplifies the protocol as a command set via the usb bulk transfer pipe. a support library, lib ft4222 , is defined for the FT4222H and is responsible for communicating with this protocol engine. wi th related apis ( application programming interface) defined in lib ft4222 , th is control engine provides a very flexible usb bri dge for spi and i 2 c bus access suitable for a wide range of applications. o tp controller + internal otp memory. the internal o tp memory provide s storage for vend o r configuration data . this vend o r config u r a tion area, named as user area, is used to store usb vendor id (vid), product id (pid), device serial number, product description string and various other usb configuration descriptors. it is also used to configure the function pin s capability . for further d etails refer to section 9 . this user area in the internal o tp memory is available to system designers to allow storing additional data from the user application over usb . the internal o tp memory can be progra mmed in circuit, over usb wit h an external voltage requirement on vpp pin (6.5v) . the descriptors can be programmed using the ftdi utility software called ft_ prog, which can be downloaded from ftdi utilities on the ftdi website ( http://www.ftdichip.com/support/utilities.htm#ft_ prog ). 5v - 3.3v - 1.8v ldo regulator. the ldo will regulate out 2 refer e nce voltages for us e within the FT4222H. the +3.3v ldo regulator generates the +3.3v reference voltage for driving the usb transceiver cell output buffers. it requires an external decoupling capacitor to be attached to the vout 3v3 regulator output pin. another + 1.8v ldo regulator generates the + 1.8v reference voltage for driving the internal core of the ic. por reset generator . por is t he integrated power on reset generator cell pr ovid ing a reliable power - on reset to the device internal c ircuitry at power up. the re is also a reset n input pin allow ing an ex ternal device to reset the ft42 2 2h . reset n can be tied to vccio (+3.3v) if not being used. embedded bcd detection. supports batte ry charger detection . the bcd_det pin will be active if the device is connected to a dedicated c harger instead of a standard usb host . r efer to section 7.5 for a n example application circuit .
copyright ? 201 5 future technology devices international limited 14 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 5 ft 4222h chip mode configuration and spi/ i 2 c inte r face 5.1 chip mode configuration the ft 4222h has 4 configuration modes selected by {dcnf1, dcnf0}. the c hip configuration mode will determine the number of usb interface s for data stream s and for gpio control. the d ata stream interface is for data transfer between the usb2. 0 host and the spi/ i 2 c device. the purpose of the gpio interface is for fully controll ing the gpios. the following table shows the pin functions corresponding to the chip configuration mode. table 5 . 1 ft4 222h pin functions on chip configuration mode *one of the spim, spis, i 2 c function is selected, the ot her 2 functions will be disable d note that gpiox pins cannot be controlled by the software driver w hen gpiox pins play the role as spim ssxo, i 2 c scl/sda , susp or wake. chip configuration only determine s the number of interface/function s supported but do not decide which bus interface (spi/ i 2 c /gpio) or which role ( master/slave) that the FT4222H will take. the u ser can use the initial isation apis provide d by the support library , lib ft4222 , to configure which interface and role will be taken. the support library for FT4222H , lib ft4222 , which is base d on d2x x, provides high - level and convenient apis ( application programming interface) to speed up user appli cation development. for further d etails refer to the user guide for libft4222 .
copyright ? 201 5 future technology devices international limited 15 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 5.2 spi bus interface 5.2.1 spi pin definition the quad spi function in the FT4222H is a fully confi gurable spi master/slave device . user s can utilize the api in lib ft4222 , ft4222 _spim aster _ init or ft4222 _spis lave _ i nit , to select in which mode (master or slave) the FT4222H will function . when the FT4222H is set as a usb - to - sp i bridge function, and chip configuratio n mode is chosen , the pins of the FT4222H will be m apped accordingly . t he spi related pins are ? clock C sck (pin - 8) , 4 types of transfer formats supported, details refer to section5. 2.2 ? data C m iso (pin - 9) , data transfer from slave to master for single mode, or data bus bit - 1 for dual and quad mode C mo si (pin - 10) , data transfer from master to slave for single mode, or data bus bit - 0 for dual and quad mode C io2 (pin - 11), data bus bit - 2 for quad mode C io3 (pin - 12 ), data bus bit - 3 for quad mode ? slave selection when q uad spi acts as spi m aster C ss0o (pin - 17 ), slave selection to slave device - 0 C ss1o (pin - 13 ), slave selection to slave devi ce - 1 C ss2o (pin - 14 ), slave selection to slave device - 2 C ss3o (pin - 15 ), slave selection to slave device - 3 ? slave selection when q uad spi acts as spi slave C ss (pin - 32 ), slave selection for spi master control. must tie h igh when q uad spi a cts as spi master 5.2.2 spi bus protocol the q uad spi allows spi data transfers in three types of bit width: ? single spi transfer C standard data transfer format C data is read and written simultaneously ? dual spi t ransfer /receive - data is transferred out or re ceived in on 2 spi lines simultaneously ? quad spi transfer /receive C data is transferred out or received in on 4 spi lines simultaneously the operating bit width in single, dual or quad mode c an a lso be determined by these 2 apis, ft4222 _spim aster _ini t and ft4222 _spis lave _init, which are defined in lib ft4222 when the spi function is enable d and selected.
copyright ? 201 5 future technology devices international limited 16 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 when the FT4222H is operating as an spi master or slave device , quadspi can transfer data in single bit mode with full - duplex trans mission. figure 5.1 shows the basic protocol in single transfer mode figure 5 . 1 q uad spi bus protocol when transferring in single mode q uad spi can operate in dual or quad transfer mode when q uad spi is programm ed as an spi master. these multi - bit transfer mode s can speed up the data transfer rate between q uad spi and the spi slave device supporting the multi - bit transfer. figure5. 2 shows the bus protocol in dual or quad mode figure 5 . 2 q uad spi bus pro tocol when transferring in quad mode
copyright ? 201 5 future technology devices international limited 17 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 5.2.3 sck format software can select any of four combinations of serial clock (sck) phase and polarity. the clock polarity is specified by the cpol control bit, which selects an active high or activ e low clock and has no significant effect on the transfer format. the clock phase (cpha) control bit selects one of two fundamentally different transfer formats. the clock phase and polarity should be identical for the master spi device and the communicati ng slave device. in some cases, the phase and polarity are changed between transfers to allow a master device to communicate with peripheral slaves having different requirements. the flexibility of the spi system on the q uad spi allows direct interface to a lmost any existing synchronous serial peripheral. user s can also use the ft4222 _spim aster _init api w hich is defined in the support library lib ft4222 to select the operating phase and polarity of sck. 5.2.3.1 cpha =0 transfer format figure 5.3 shows a timing diagram of an spi transfer where cpha is equal to 0. two waveforms are shown for sck: one for cpol equal to 0 and another for cpol equal to 1. the diagram may be interpreted as a master or slave timing diagram since the sck, master in/slave out ( m iso), and master out/slave in ( mo si ) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is t he output from the master. figure 5 . 3 sck transfer fo rmat when cpha=0 5.2.3.2 cpha =1 t r ansfer format figure 5.4 is a timing diagram of an spi transfer where cpha equal to 1. two waveforms are shown for sck: one for cpol equal to 0 and another for cpol equal to 1. the diagram may be interpreted as a master or slave t iming diagram since the sck, miso, and mo si pins are directly connected between the master and the slave. the miso signal is the output from the slave, a nd the mosi signal is t he output from the master. the ss line is the slave select input to the slave . figure 5 . 4 sck transfer format when cpha= 1
copyright ? 201 5 future technology devices international limited 18 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 5.2.4 spi timing figure 5 . 5 spi timing the tabl e5.2 shows the timing information for quadspi. the result is under the condition of all the related pins with 5pf loading. t6 is the required setup time to the related sck edge for the input data path of quadspi. the min i mum value of t4 means that the guar anteed setup time to the related sck edge for connected device to fetch data from quadspi. the maximum value of t6 means that data can be accepted correctly by quadspi with 5pf pin loading assumed. if the pin load is larger, the timing should be considered conservatively. parameter min (ns) typ(ns) max(ns) description t1 @master t2+t3 sck period when q uad spi as master t1@slave 50 acceptable sck period when q uad spi as slave device t2 12.5 sck high , related to the operating clock and ratio t3 12.5 sclk low , related to the operating clock and ratio t4 t3 - 2.0 t3 - 1.1 data output path: setup time to corresponding sck edge t5 t2+0.1 t2+0.6 data output path: hold time to corresponding sck edge t6 4.9 9.8 data input path: required setup time to corr esponding sck edge t7 0.1 data input path: required hold time to corresponding sck edge t8 6*t1 ss xo setup time to 1 st sck period boundary t9 6*t1 ss xo hold time from last sck period boundary t10@master 6*t1 idle time on sck between byte bounda ry when master t10@slave 0 idle time on sck between byte boundary when slave table 5 . 2 spi timing for vccio=3.3v with 5pf output pin load
copyright ? 201 5 future technology devices international limited 19 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 table5.3 shows the timing information for quadspi with vccio e qual to 1.8v and with 5pf loading on all the related pins . t he required setup time for input path is increasing since vccio=1.8v. the maximum operating frequency of sck is recommended not exceeded 30mhz. parameter min (ns) typ (ns) max (ns) description t1 @ master t2+t3 sc k period when q uad spi as master t1 @slave 50 acceptable sck period when q uad spi as slave device t2 1 6.67 sc k high , related to the operating clock and ratio t3 1 6.67 sclk low , related to the operating clock and ratio t4 t 3 - 2. 1 t3 - 1. 2 data output path: setup time to corresponding sck edge t5 t2+0.1 t2+ 0.6 data output path: hold time to corresponding sck edge t6 8.6 16 .5 data input path: required setup time to corresponding sck edge t7 0.1 data input path: required hold time to corresponding sck edge t8 6*t1 ss xo setup time to 1 st sck period boundary t9 6*t1 ss xo hold time from last sck period boundary t10@master 6*t1 idle time on sck between byte boundary when master t10@slave 0 idle time on sck between byte bound ary when slave table 5 . 3 spi timing for vccio= 1 . 8 v with 5pf output pin load
copyright ? 201 5 future technology devices international limited 20 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 5.3 i 2 c bus interface i 2 c (inter integrated circuit) is a multi - master serial bus invented by philips. i 2 c uses two bi - directional ope n - drain wires called serial data (sda) and serial clock (scl). common i2c bus speeds are standard mode (sm) with bit rate up to 100 kbit /s , fast mode (fm) with bit rate up to 400 kbit /s , fast mode plus (fm+) with bit rate up to 1 mbit/s , and high speed mod e (hs) with the bit rate up to 3.4 mbit/s . an i 2 c bus node can operate either as a master or a slave: ? master node C issues the clock and addresses slaves ? slave node C receives the clock line and address. the ft 4222h can operate as a master or slave, and is capable of being set to the speed modes defined in the i 2 c bus specification . besides the speed mode defined in the i 2 c standard specification, the i 2 c controller of the FT4222H can s upport flexible scl frequenc ies de fin ed by the following function ??? ???? = ????????? ????? ????????? ? ? ( ? + ? ) ? = ? ?? ? ; ? = ? , ? , ? , , ??? when the target frequ ency is below 100 khz , m will be equal to 8; otherwise, m will be equal to 6. for example, to generat e a 2.5mhz frequency on scl, m will be selected as 6. then with an operating clock frequency equal to 60mhz the user can set n as 3. the scl frequency for i 2 c master mode can be set vi a the ft4222 _i2cm aster _ init command defined in the support library , lib ft4222 . r efer to the user guide for libft4222 for further details . 5.3.1 i 2 c pi n definition the i 2 c function in the FT4222H is a fully confi gurable i 2 c mas ter/slave device . when the chip configuration is set as cnfmode0 or cnfmod e 3 and the usb - to - i 2 c bridge function is enable d via the ft4222 _i2cm aster _init api which is def ined in the support library lib ft4222 . t he pins of the FT4222H will be mapped according ly . the i 2 c pins are ? clock C scl (pin - 13 ) , as clock output with open - drain design when i 2 c bus is set as master. as clock input when i 2 c bus is set as slave. ? data C sda (pin - 14 ) , command/address/data transfer between master and slave with open - drain desig n 5.3.2 i 2 c b us protocol there are four potential modes of operation for a given bus device, although most devices only use a single role (master or slave) and its two modes (transmit and receive): ? master transmit C sending data to a slave ? master receive C rece iving data from a slave ? slave transmit C sending data to a master ? slave receive C receiving data from the master the following figure shows the basic i 2 c bus protocol figure 5 . 6 i 2 c bus protocol
copyright ? 201 5 future technology devices international limited 21 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 the maste r is initially in master transmit mode by sending a start bit followed by the 7 - bit address of the slave it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write(0) to or read(1) from the slave. if th e slave exists on the bus then it will respond with an ack bit (active low for acknowledged) for that address. the master then continues in either transmit or receive mode (according to the read/write bit it sent), and the slave continues in its complement ary mode (receive or transmit, respectively). the address and the data bytes are sent most significant bit first. the start bit is indicated by a high - to - low transition of sda with scl high; the stop bit is indicated by a low - to - high transition of sda with scl high. if the master wishes to write to the slave then it repeatedly sends a byte with the slave sending an ack bit. (in this situation, the master is in master transmit mode and the slave is in slave receive mode.) if the master wish to read from the slave then it repeatedly receives a byte from the slave, the master sends an ack bit after every byte but the last one. (in this situation, the master is in master receive mode and the slave is in sl ave transmit mode.) the master then ends transmission with a stop bit, or it may send another start bit if it wishes to retain control of the bus for another transfer (a "combined message"). i2c defines three basic types of message, each of which begins wi th a start and ends with a stop: ? single message where a master writes data to a slave; ? single message where a master reads data from a slave; ? combined messages, where a master issues at least two reads and/or writes to one or more slaves in a combined mess age, each read or write begins with a start and the slave address. after the first start, these are also called repeated start bits; repeated start bits are not preceded by stop bits, which is how slaves know the next transfer is part of the same message. user s can refer to the i 2 c specification for more information on the protocol. 5.3.3 i 2 c slave address when the FT4222H is configured as a usb to i2c master bridge, it must be able to issue any value of 7 - bits slave address. user s can issue i 2 c command s to read or write data to a slave via the command s ft4222 _i2cm aster _read and ft4222 _i2cm aster _write, define d in the support library lib ft4222 , with a corresponding slave address. when the FT4222H is configured as a usb to i2c slave bridge, the slave address may be defined by the user . this slave address parameter is define d by default as 40h and can be set once in the i2c slave address parameter which is defined in the user data area of the otp memory. for further d etails refer to section 9. 5.3.4 i 2 c timing figure 5 . 7 i 2 c bus timing
copyright ? 201 5 future technology devices international limited 22 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 parameter min(ns) typ(ns) m ax (ns) description t 0@48mhz 20.833 t0 is the period when operating clock=48mhz t0@60mhz 16.666 t0 is the period when operating clock=60mhz t0@80mhz 12.500 t 0 is the period when operating clock=80mhz timing for i 2 c master t1 @sm 16*t0 8*(1+n)*t0 sck period when i 2 c as master with standard speed mode(sm) t1 @fm/hm 12*t0 6*(1+n)*t0 sck period when i 2 c as master with fm, fm+, hs speed mode t2 8*t0 4*(1+n)*t0 sck high pulse width when i 2 c as master with standard speed mode(sm) t2 4*t0 2*(1+n)*t0 sck high pulse width when i 2 c as master with fm, fm+, hs speed mode t3 2*(1+n)*t0 sda output setup time to scl rising edge when i 2 c as master t4 2*(1+n)*t0 sd a output hold time to scl falling edge when i 2 c as master t5 2 c as master t6 2 c as master t7 2*(1+n)*t0 start bit setup time to scl falling edge t8 4*(1+n)*t0 start bit hold time to scl falling edge t9 2*(1+n)*t0 stop bit setup time to scl rising edge t10 2*(1+n)*t0 stop bit hold time to scl rising edge t11 4*(1+n)*t0 bus free time between start and stop bit timing for i 2 c slave t1 12*t0 acceptable scl period when i 2 c as slave device t2 1*t0 scl high pulse width requirement when i 2 c as slave t3 2 c as slave device t4 1*t0 input hold time requirement from sda to scl falling edge when i 2 c as slave device t5 t8 - t6 sda output setup time to scl rising edge t6 3*t0 4*t0 5*t0 sda o utput hold time to scl falling edge table 5 . 4 i 2 c timing for vccio=3.3v note that n can be ranged from 1 to 255
copyright ? 201 5 future technology devices international limited 23 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 5.4 gpios when the configuration mode of the ft 4222h is set as cnfmode0 or cnfmode1, a gpio pipe w ill be enabled. these 4 pins, gpio0, gpio1, gpio2 and gpio3, can be set as general purpose input/output pins or other functions such as multi - channel spi slave selections, i 2 c interface, suspend out indicator, remote wake up input or interrupt . if no funct ions are set on these pins, the default function is gpio. the u ser can set the direction for gpios via the api, ft4222 _gpio_ init, defined in libft4222 . t he logic level can be read and writte n via the apis , ft4222 _gpio_read and ft4222 _gpio_write . the ft42 22h also provides an interrupt input source for the user to utilize . gpio3(pin - 16) can be set as an interrupt input source via the api , ft4222 _set wakeupinterrupt , defined in lib ft4222 . gpio3 can be set as a rising edge or falling edge triggered interrupt v ia ft_prog. the related parameter defined in the user area is named as the interrupt trigger edge. the default setting is rising edge triggered. detail s can be referenced in table9.1 . figure5.8 shows the differ ent behaviour when gpio3 acts as gpio or interrupt. the i nterrupt is set by default as rising edge triggered. user s can choose either one for their application. figure 5 . 8 different status when gpio3 set as gpio or interrupt input
copyright ? 201 5 future technology devices international limited 24 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 6 devices characteristics and ratings 6.1 absolute maximum ratings the absolute maximum ratings for the ft 42 22 h devices are as follows. these are in accordance with the absolute maximum rating system (iec 60134). exceeding these may cause permanent damage to the device. parameter value unit conditions storage temperature - 65c to 150c degrees c floor life (out of bag) at factory ambient (30c / 60% relative humidity) 168 hours (ipc/jedec j - std - 0 33a msl level 3 compliant)* hours ambient operating temperature (power applied) - 40c to 85c degrees c mttf ft 42 2 2 h tbd hours vcc in supply voltage - 0.3 to +5 . 5 v vccio io voltage - 0.3 to + 4.0 v vpp supply voltage 6.5 0.25 v dc input voltage C usbdp and usbdm - 0.5 to +3.63 v dc input voltage C high impedance bi - directionals (powered from vccio) - 0.3 to + (vccio+0.5v) v dc output current C outputs 100 ** ma table 6 . 1 absolute maximum ratings * if devices are stored out of the packaging beyond this time limit the devices should be baked before use. the devices should be ramped up to a temperature of + 125 c and baked for up to 17 hours . ** this dc output current is also the power supply sour ce for FT4222H operati on . if it must be the source for other component on the system, it only can supply 25ma or less. 6.2 esd and latch - up specifications description specification human body mode (hbm) > 2kv machine mode (mm) > 200v charged device m ode (cdm) > 500v latch - up > 200ma table 6 . 2 esd and latch - up specifications
copyright ? 201 5 future technology devices international limited 25 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 6.3 dc characteristics dc characteristics (ambient temperature = - 40c to + 85c ) parameter description minimum typical maximum units conditions vcc 1 vcc in operating supply voltage 4.5 5 5.5 v vccin is supplied with 5v 2.97 3.3 3.63v v vccin is supplied with 3.3v vcc 2 vccio operating supply voltage 2.97 3.3 3.63 v vccio is supplied with 3.3v 2.25 2.5 2.75 v vccio is supplie d with 2.5v 1.62 1.8 1.98 v vccio is supplied with 1.8v icc1 operating supply current 50 52 ma normal operation at 24 mhz 62 64 ma normal operation at 48mhz 68 70 ma normal operation at 60mhz 78 80 ma normal operation at 80mhz icc2 suspend supply current 375 460 a 377 4 6 5 a 386 419 a 2 c master 388 456 a 2 c slave 3v3 3.3v regulator output 2.97 3.3 3.63 v vcc in must be greater than 3v3 otherwise v out 3v3 is an input which must be driven with 3.3v table 6 . 3 operating voltage and current
copyright ? 201 5 future technology devices international limited 26 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 parameter description minimum typical maximum units conditions voh output voltage high 2.97 vccio vcc io v ioh = +/ - 2ma i/o drive strength* = 4ma 2.97 vccio vccio v i/o drive strength* = 8ma 2.97 vccio vccio v i/o drive strength* = 12ma 2.97 vccio vccio v i/o drive strength* = 16ma vol output voltage low 0 0.4 v iol = +/ - 2ma i/o drive strength* = 4ma 0 0.4 v i/o drive strength* = 8ma 0 0.4 v i/o drive strength* = 12ma 0 0.4 v i/o drive strength* = 16ma vil input low switching threshold 0.8 v lvttl vih input high switching threshold 2.0 v lvttl vt switching threshold 1. 49 v lv ttl vt - schmitt trigger negative going threshold voltage 1.1 5 v vt+ schmitt trigger positive going threshold voltage 1.6 4 v rpu input pull - up resistance 40 75 190 k? vin = 0 rpd input pull - down resistance 40 75 190 k? vin =vccio iin input leakage current - 10 +/ - 1 10 a vin = 0 ioz tri - state output leakage current - 10 +/ - 1 10 a vin = 5.5v or 0 table 6 . 4 i/o pin char acteristics vccio = +3.3v (except usb phy pins) * the i/o drive strength and slow slew - rate are configurable in the o tp memory.
copyright ? 201 5 future technology devices international limited 27 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 parameter description minimum typical maximum units conditions voh output voltage high 2.25 vccio vccio v ioh = +/ - 2ma i/o d rive strength* = 4ma 2.25 vccio vccio v i/o drive strength* = 8ma 2.25 vccio vccio v i/o drive strength* = 12ma 2.25 vccio vccio v i/o drive strength* = 16ma vol output voltage low 0 0.4 v iol = +/ - 2ma i/o drive strength* = 4ma 0 0.4 v i/o d rive strength* = 8ma 0 0.4 v i/o drive strength* = 12ma 0 0.4 v i/o drive strength* = 16ma vil input low switching threshold 0.8 v lvttl vih input high switching threshold 1 . 7 v lvttl vt switching threshold 1.1 v lvttl vt - schmitt trigger negative going threshold voltage 0.8 v vt+ schmitt trigger positive going threshold voltage 1. 2 v rpu input pull - up resistance 40 75 190 k? vin = 0 rpd input pull - down resistance 40 75 190 k? vin =vccio iin input leakage current - 10 +/ - 1 10 a vin = 0 ioz tri - state output leakage current - 10 +/ - 1 10 a vin = 5.5v or 0 table 6 . 5 i/o pin char acteristics vccio = +2.5 v (except usb phy pins) * the i/o drive strength and slow slew - rate are configurable in the o tp memory.
copyright ? 201 5 future technology devices international limited 28 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 parameter description minimum typical maximum units conditions voh output voltage high 1.62 vccio vccio v ioh = +/ - 2ma i/o d rive strength* = 4ma 1.62 vccio vccio v i/o drive strength* = 8ma 1.62 vccio vccio v i/o drive strength* = 12ma 1.62 vccio vccio v i/o drive strength* = 16ma vol output voltage low 0 0.4 v iol = +/ - 2ma i/o drive strength* = 4ma 0 0.4 v i/o d rive strength* = 8ma 0 0.4 v i/o drive strength* = 12ma 0 0.4 v i/o drive strength* = 16ma vil input low switching threshold 0. 63 v lvttl vih input high switching threshold 1. 17 v lvttl vt switching threshold 0.77 v lvttl vt - schmitt trig ger negative going threshold voltage 0.557 v vt+ schmitt trigger positive going threshold voltage 0.893 v rpu input pull - up resistance 40 75 190 k? vin = 0 rpd input pull - down resistance 40 75 190 k? vin =vccio iin input leakage current - 10 +/ - 1 10 a vin = 0 ioz tri - state output leakage current - 10 +/ - 1 10 a vin = 5.5v or 0 table 6 . 6 i/o pin char acteristics vccio = +1.8 v (except usb phy pins) * the i/o drive strength and slow slew - rate are configurable in the o tp memory.
copyright ? 201 5 future technology devices international limited 29 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 dc characteristics (ambient temperature = - 40c to +85c) parameter description minimum typical maximum units conditions v phy , v pll phy operating supply voltage 3.0 3.3 3.6 v 3.3v i/o i ccphy phy operating supply current --- 30 60 ma high - speed operation at 480 mhz i ccphy (susp) phy suspend supply current --- 2 10 2 50 a usb suspend table 6 . 7 usb phy operating voltage and current parameter description minimum typical maximum units conditions v hsd i ff high speed differential input voltage sensitivity 300 m v v i(dp) C v i(d m) measure at the connection of an application circuit v hscm common mode voltage range of high speed data signalling - 50 500 m v v hssq high speed squelch detection threshold 100 m v squelch is detected 150 mv squelch is not detected v hsdsc high s peed disconnection detection threshold 625 m v disconnection is detected 525 mv disconnection is not detected v hsoi high speed idle level output voltage(differential) - 10 10 mv v hsol high speed low level output voltage(differential) - 10 10 mv v hsol high speed high level output voltage(differential) 360 400 mv v chirpj chirp - j output voltage(differential) 700 11 00 mv v chirpk chirp - k output voltage(differential) - 900 - 500 mv v di full speed differential input voltage sensitivity 0.2 v v i (dp) C v i(dm) v cm differential common mode voltage range of full speed data signalling 0.8 2.5 v
copyright ? 201 5 future technology devices international limited 30 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 v se full speed single - ended receiver threshold 0.8 2.0 v v olphy full speed low - level output voltage 0 0.3 v v ohphy full speed high - level output volta ge 2.8 3.6 v table 6 . 8 usb i/o pin (dp, dm) characteristics 6.4 o tp memory reliability characteristics the internal 128 bytes o tp memory has the following reliability characteristics: parameter value unit dat a retention 1 0 years write cycle 1 times read cycle unlimited times table 6 . 9 o tp memory characteristics
copyright ? 201 5 future technology devices international limited 31 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 7 FT4222H configurations the following sections illustrate possible usb power configurations for the ft 4222h . 7.1 usb bus powered configuration figure 7 . 1 bus powered configuration figure 7 . 1 i llustrates the ft 42 22 h in a typical usb 2.0 bus powered design configuration. a usb bus powered device gets its power from the usb bus. basic rules for usb bu s power ed devices are as follows i) on plug - in to usb, the device should draw no more current than 100ma. ii) in usb suspend mode the device should draw no more than 2.5ma . iii) a bus pow ered , high power usb device (one that draws more than 100ma) can use susp_out(pin - 15) as a power disable function and use it to keep the current below 2.5ma on usb suspend. iv) a device that consumes more than 100ma cannot be plugged into a usb bus powered hub . v) no device can draw more than 500ma from the usb bus. the power descriptors in the internal o tp memory of the ft 42 22 h should be programmed to match the current drawn by the device. a ferrite bead is connected in series with the usb power supply to reduce emi noise from the ft 42 22 h and associated circuitry being radiated down the usb cable to the usb host. the value of the ferrite bead depends on the total current drawn by the application. a suitable range of ferrite beads is available from steward ( www.steward.com ) , for example laird technologies part # mi0805k400r - 10.
copyright ? 201 5 future technology devices international limited 32 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 7.2 self powered configuration with 5v source in put figure 7 . 2 self powered configuration with 5v source input figure 7 . 2 illustrates the ft 42 22 h in a typical usb 2.0 self - powered configuration. a usb self - powered device gets its pow e r from its own power supply, 5v , and does not draw current from the usb bus. the basic rules for usb self - powered devices are as follows C i) a self - powered device should not force current down the usb bus when the usb host or hub controller is powered down. ii) a self - powered device can use as much current as it needs during normal operation and usb suspend as it has its own power supply. iii) a self - powered device can be used with any usb host, a bus powered usb hub or a self - powered usb hub. the power descriptor in the internal o tp memory of the ft 42 22 h should be programmed to a value of zero ( self - powered ). in order to comply with the first requirement above, the usb bus power ( usb connector pin 1) is used to control the vbus_ det pin of the ft 42 22 h device. when the usb host or hub is powered up a n internal 1.5k resistor on dp is pulled up to +3.3v , thus identifying th e device to the usb host or hub. when the usb host or hub is powered off, the vbus_ det pin will be low and the ft 42 22 h is held in a suspend state. in this state the internal 1.5k resistor is not pulled up to any power supply (hub or host is powered dow n), so no current flows down dp via the 1.5k pull - up resistor. failure to do this may cause some usb host or hub controllers to power up erratically.
copyright ? 201 5 future technology devices international limited 33 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 7.3 s elf powered configuration with 3.3 v source in figure 7 . 3 self powered configuration with 3.3v source input figure 7 . 3 illustr ates the ft42 2 2h in a typical usb self - powered configuration similar to figure 7 . 2 error! reference source not found. . the difference here is that the self - power source is 3.3v. if using 3.3v as power source in, remember to connect it to vout3v3 to supply actual operating voltage to usb2.0 phy.
copyright ? 201 5 future technology devices international limited 34 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 7.4 crystal oscillator configuration figure 7 . 4 recommended ft42 2 2h crystal oscillator configuration. figure 7 . 4 illu strates how to connect the ft42 2 2h with a 12mhz 0.003% crystal. in this case loading capacitors should to be added between osci, osco and gnd as shown. a value of 27pf is shown as the capacitor in the example C this will be good for many crystals but it is recommended to select the loading capacitor value based on the manufacturers recommendations wherever possible. it is recommended to use a parallel cut type crystal. it is also possible to use a 12 mhz osci llator with the ft42 2 2h. in this case the output of the oscillator would drive x sci, and x sco should be left unconnected. the oscillator must have a cmos output drive capability. parameter description minimum typical maximum units conditions x sci vin inp ut voltage 2.97 3.30 3.63 v fin input frequency 12 mhz +/ - 30ppm ji cycle to cycle jitter < 150 p s table 7 . 1 x sci input characteristics
copyright ? 201 5 future technology devices international limited 35 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 7.5 usb battery charging detection a n addition to the usb specif ication ( http://www.usb.org/developers/docs/devclass_docs/bcv1.2_070312.zip ) is to allow for additional charging profiles to be used for charging batteries in portable devi ces. these charging profiles do not enumerate the usb port of the peripheral. t he ft 42 22 h device will detect that a usb compliant dedicated charging port (dcp) is connected. once detected while in suspend mode a battery charge detection signal is then prov ide d to allow external logic to switch to charging mode as opposed to operation mode. figure 7 . 5 usb battery charging detection to use the ft 42 22 h with battery charging detection , the bcd_det pin acts as b cd charger output to switch the external charger circuitry on. if the charging circuitry requires an active low signal to enable it, t he polarity of bcd_det can be configured in the vender configuration area of internal o tp memory . when connected to a usb compliant dedicated charging port (dcp, as opposed to a standard usb host) the device usb signals will be shorted together. the bcd charger signal will bring the ltc4053 out of suspend and allow battery charging to start. the charge current in the example above is 1a as defined by the resistance on the prog pin. to calculate the equivalent resistance on the ltc4053 prog pin select a charge current, then res = 1500v/i chg for more confi guration options of the ltc4053 refer to : section4.3 example with 1 cbus pin in an_175_battery charging over usb note: if the ft 42 22h is connected to a standard host port such that the device i s enumerated , the signal bcd_det is inactive , ltc4053 is in shut down condition and the charging function will not be enable d .
copyright ? 201 5 future technology devices international limited 36 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 8 application examples the following diagram s show the possible application s of the ft 42 22 h . in figure 8 . 1 , a control ic with an spi slave interface but without a usb device interface can easily connect to usb by integrating the FT4222H i nto the system. with ftdi s mature and stable d2xx driver, and easy to use support library , lib ft4222 , the ft4222 h can easily connect an application to usb . figure 8 . 1 application example 1 in figure 8 . 2 , a control ic with an spi master interface but without a usb upst ream port (usb device interface ) can easily connect to usb by integrating the FT4222H i nto the system. with a single spi slave interface defined in FT4222H and easy to use api defined in lib ft4222 , it is easy to connect an application to usb via FT4222H. figure 8 . 2 application example 2
copyright ? 201 5 future technology devices international limited 37 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 in figure 8 . 3 , a control ic with an i 2 c slave interface but without a usb device interface can easily connect to usb b y integrating the FT4222H i nto the system. with ftdi s mature and stable d2xx driver, and easy to use support library , lib ft4222 , the ft4222 h can easily connect an application to usb . with a suitable pull - high resistor value on i 2 c bus, the transfer speed at this i 2 c interface can be spe d up to the hs mode defined in i 2 c specification. figure 8 . 3 application example 3 in figure 8 . 4 , a control ic with an i 2 c maste r interface but without a usb upstream port (usb device interface ) can easily connect to usb by integrating the FT4222H i nto the system. with an i 2 c slave interface defined in the FT4222H and easy to use api defined in lib ft4222 , it is easy to connect an a pplication to usb via the FT4222H. with a suitable pull - high resistor value on i 2 c bus, the transfer speed at this i 2 c interface can be speed up to the hs mode. figure 8 . 4 application example 4
copyright ? 201 5 future technology devices international limited 38 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 9 internal o t p memory configuration the ft 4222h includes an internal o tp memory which holds the usb configuration descriptors, other configuration data for the chip and also user data areas. following a power - on reset or a usb reset the ft 4222h will scan its internal o tp memory and read the usb configuration descriptors stored there. in many cases, the default values programmed into the o tp memory will be suitable and no re - programming will be necessary. the defaults can be found in section 9.1 . the o tp memory in the ft 4222h can be programmed over usb if the values need to be changed for a particular application. further details of this are provided from section 9.2 onwards. users w ho do not have their own usb vendor id but who would like to use a unique product id in their design can apply to ftdi for a free block of unique pids. see tn_100 C usb vendor id/product id guidelines for more details . 9.1 default values the default factory programmed values of the internal o tp memory are shown in table9.1. parameter default value notes device type ft4222 h read - only. indicate the chip i s FT4222H. usb vendor id (vid) 0403h usb vendor id. defined in the usb device descriptor . the format is 16 - bit hex coded and d efault is set as ftdi vid . usb product i d (pid) 60 1 c h usb product id. defined in the usb device descriptor the format is 16 - bit hex coded and default is set as ftdi vid . usb version 0200 h read - only. returns the usb 2.0 device descript or t o the host. note: FT4222H is a hi - speed usb2.0 device. if the connected host/hub is full speed only, the FT4222H will operate at ful l speed without changing this usb version parameter to usb1.1. power source bus powered define whether the power source is from the usb bus or a local source. max bus power current 10 0ma the max power that will be drawn from vbus when using bus power . range from 0~500ma. if the power source is defined as self - power ed , it must be set as 0ma. remote wake up enable define if the FT4222H support s remote wake up or not. manufacturer name ftdi describing the manufacturer. a string descriptor defi ned in usb device descriptor s product description ft4222 describing the product. a string descriptor defined in usb device descriptor s serial number enabled? no enable the string descriptor for serial number or not.
copyright ? 201 5 future technology devices international limited 39 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 parameter default value notes serial number none a unique seria l number is generated and programmed into the o tp memory . refer to the utility ft_prog for details enable suspend out e nable set gpio2(pin - 15) as usb suspend indicator suspend out polarity active - high set the polarity on gpio2 pin for indicating suspend out. default is set as active - high. i 2 c slave address 40h set the i 2 c slave address when i 2 c slave function is enabled. range from 00h ~ 7fh spi drive strength 4ma adjustable d rive strength for spi related pins sck, miso/mosi/io2/io3, ss0o . drive strengt h can be set as 4ma, 8ma, 12ma and 16ma spi weak pullup/pulldown d isable enable the weak pullup / pulldown resistor on the pin ss(pin - 32). default is disable d (without any pull). spi slew rate enable? d isable set the slew rate control for spi related pin s sck, miso, mosi, ss0o, io2, io3. default is disabled spi suspend mode d isable (tri - state) mode selection for i/o status of spi related pins sck, miso, mosi, io2, io3, ss0o when usb suspend s . refer to table 5.8 for defaults. spi suspend no change d efine the behaviour of spi related pins miso, mosi, io2/io3, ss0o when usb suspend happens . behaviour can be set as no change, push - high or push - low when spi suspend mode is set as enable spi pin control. gpio drive strength 4ma adjustable d rive strength for gpio related pins gpio0, gpio1, gpio2, gpio3. drive strength can be set as 4ma, 8ma, 12ma and 16ma gpio open drain d isable set the behaviour of gpio pins as open - drain. default is disabl ed(gpio acts as push - pull mode) gpio weak pullup/pulldown d isable enable the weak pullup / pulldown resistor on the pins gpio0, gpio1, gpio2, gpio3. default is disabled (without any pull). gpio suspend input(tri - state) d efine the behaviour of gpio relate d pins gpio0, gpio1 , gpio 2, gpio 3 wh en suspend happens . pins can be set as no change, input as tri - state, push - high or push - low bcd _det function dis able ? no battery charger detection function can be disabled on bcd_det pin (pin - 31). bcd _ det drive strengt h 4ma adjustable d rive strength for bcd_det pin. drive strength can be set as 4ma, 8ma, 12ma and 16ma bcd _det polarity active - high set the polarity on bcd_det pin for indicating battery charge detected. default is set as active - high.
copyright ? 201 5 future technology devices international limited 40 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 parameter default value notes interrupt trigger ed ge r ising edge define the interrupt trigger edge when gpio3 (pin - 16) is set as intr/wakeup function. default is rising - edge triggered. table 9 . 1 default internal o tp memory configuration
copyright ? 201 5 future technology devices international limited 41 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 9.2 method of programming the o tp memory 9.2.1 programming the otp memory over usb the otp memory on a FT4222H device can be programmed over usb. this method is the same as for the mtp on other ftdi devices such as the ft - x series . please note that in order to program otp, the FT4222H requires an additional p rogramming voltage ( 6.5v ) on its vpp pin . the programming board , umft4222prog, supplies an easy connection bridge between the FT4222H and a usb host for boosting the vbus up to 6.5v and for communicating with the program ming utility ft_pro g. further details may be found in the datasheet for umft4222prog , the FT4222H p rogramming m odule . the ft_prog utility is provided free - of - charge from the ftdi website, and can be found at the link below. the user guide is also available at this link. http://www.ftdichip.com/support/utilities.htm#ft _prog additionally, d2xx commands can be used to program the otp memory from within the user applications. for more information on the commands available, please see the d2xx programmers guide below. http://www.ftdichip.com/support/documents/programguides/d2xx_programmer's_guide(ft_000071).p df
copyright ? 201 5 future technology devices international limited 42 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 10 package parameters the ft 42 2 2h is available in a v qfn - 32 package . the solder reflow profile for v qfn - 32 is described in section 10.3 . 10.1 v qfn - 32 package mechanical dimensions figure 10 . 1 v qfn - 32 package dimensions the ft 42 22 h is supplied in a rohs compliant lead less v qfn - 32 package. the package is lead (pb) free, and uses a green compound. the package is fully compliant with european union directive 2002/95/ec. this package is nominally 5 .00mm x 5 .00 mm. the solder pads are on a 0. 5 mm pitch. the above mechanical drawing shows the v qfn - 32 package. all dimensions are in millimetres. the centre pad on the base of the ft 42 22 h is intern ally connected to gnd and the pcb should not have signal tracking on the top layer under this area . connect to gnd.
copyright ? 201 5 future technology devices international limited 43 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 10.2 v qfn - 32 package markings figure 10 . 2 v qfn - 32 package markings the date code format is yy ww where ww = 2 digit week number, yy = 2 digit year number. this is followed by the revision number. the code xxxxxx x x is the manufa cturing lot code ft di xxxxxxxx FT4222Hq line 1 C ftdi logo l ine 4 C date code, revision l ine 2 C wafer lot number 1 2 4 l ine 3 C ftdi part number yyww - b 9 16
copyright ? 201 5 future technology devices international limited 44 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 10.3 solder reflow profile the ft 42 22 h is supplied in a pb free v qfn - 32 package . the recommended solder reflow profile is shown in figure 10 . 3 . figure 10 . 3 ft 42 22 h solder reflow profile the recommended values for the solder reflow profile are detailed in table 10 . 1 . values are shown for both a completely pb free solder process (i.e. the ft 42 22 h is used with pb free solder), and for a non - pb free solder process (i.e. the ft 42 22 h is used with non - pb free solder). profile feature pb free solder process non - pb free solder process average ramp up rate (t s to t p ) 3c / second max. 3c / second max. preheat - temperature min (t s min.) - temperature max (t s max.) - time (t s min to t s max) 150c 200c 60 to 12 0 seconds 100c 150c 60 to 120 seconds time maintained above critical temperature t l : - temperature (t l ) - time (t l ) 217c 60 to 150 seconds 183c 60 to 150 seconds peak temperature (t p ) 260c 240c time within 5c of actual peak temperature (t p ) 20 to 40 seconds 2 0 to 4 0 seconds ramp down rate 6c / second max. 6c / second max. time for t= 25c to peak temperature, t p 8 minutes max. 6 minutes max. table 10 . 1 reflow profile parameter values critical zone: when t is in the range t to t t e m p e r a t u r e , t ( d e g r e e s c ) time, t (seconds) 25 p t = 25 o c to t t p t p t l t preheat s t l ramp up l p ramp down t max s t min s
copyright ? 201 5 future technology devices international limited 45 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 11 contact information head office C glasgow, uk future technology devices international limited unit 1, 2 seaward place, centurion business park glasgow g41 1hh united kingdom tel: +44 (0) 141 429 2777 fax: +44 (0) 141 429 2758 e - mail (sales) sales 1 @ftdichip.com e - mail (support) support 1 @ftdichip.com e - mail (general enquiries) admin1@ftdichip.com branch office C taipei, taiwan future technology devices international limited (taiwan) 2f, no. 516, sec. 1, neihu road taipei 114 taiwan , r.o.c. tel: +886 (0) 2 8791 3570 fax: +886 (0) 2 8791 3576 e - mail (sales) tw.sales1@ftdichip.com e - mail (support) tw.support1@ftdichip.com e - mail (general enquiries) tw.admin1@ftdichip.com branch office C tigard , oregon, usa future technology devices international limited (usa) 7130 sw fir loop tigard, or 97223 usa tel: +1 (503) 547 0988 fax: +1 (503) 547 0987 e - mail (sales) us.sales@ftdichip.com e - mail (support) us.support@ftdichip.com e - mail (general enquiries) us.admin@ftdichip.com branch office C shanghai, china future technology devices internation al limited (china) room 1103 , no.666 west huaihai r oad, shanghai, 200052 china tel: +86 21 62351596 fax: +86 21 62351595 e - mail (sales) cn.sales@ftdichip.com e - mail (support) cn.support@ftdichip.com e - mail (general enquiries) cn.admin@ftdichip.com web site http://ftdichip.com distributor and sales representatives please visit the sales network page of the ftdi web site for the contact details of our distributor(s) and sales representative(s) in your country. system and equipment manufacturers and designers are responsible to ensure that their systems, and any future technology devices international ltd (ftdi) devices incorporated in their systems, meet all applicable safety, regulatory and system - level per formance requirements. all application - related information in this document (including application descriptions, suggested ftdi devices and other materials) is provided for reference only. while ftdi has taken care to assure it is accurate, this informatio n is subject to customer confirmation, and ftdi disclaims all liability for system designs and for any applications assistance provided by ftdi. use of ftdi devices in life support and/or safety applications is entirely at the users risk, a nd the user agr ees to defend, indemnify and hold harmless ftdi from any and all damages, claims, suits or expense resulting from such use. this document is subject to change without notice. no freedom to use patents or other intellectual property rights is implied by the publication of this document. neither the whole nor any part of the information contained in, or the product described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright hol der. future technology devices international ltd, unit 1, 2 seaward place, centurion business park, glasgow g41 1hh, united kingdom. scotland registered company number: sc136640
copyright ? 201 5 future technology devices international limited 46 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 appendix a C references us eful application notes http://www.ftdichip.com/support/documents/appnotes/an_329_user_guide_for_libft4222.pdf http://www.ftdichip.com/support/documents/datasheets/modules/ds_umft 4222ev .pdf http://www.ftdichip.com/suppo rt/documents/datasheets/modules/ds_umft 4222prog .pdf http://www.ftdichip.com/support/utilities.htm#ft_prog http://www.ftdichip.com/support/documents/programguides/d2xx_programmer's_guide(ft_000071).p df http://www.ftdichip.com /documents/appnotes/an_107_advanceddriveroptions_an_000073.pdf http://www.ftdichip.com/documents/appnotes/an_121_ftdi_device_eeprom_user_area_usage.pdf http://www.ftdichip.com/documents/installguides.htm http://www.ftdichip.com/supp ort/documents/technicalnotes/tn_100_usb_vid - pid_guidelines.pdf http://www.ftdichip.com/support/documents/appnotes/an_175_b attery%20charging%20over%20usb %20with%20ftex%20devices.pdf http://i2c2p.twibright.com/spec/i2c.pdf http://www.usb.org/developers/docs/devclass_docs/bcv1.2_070312.zip
copyright ? 201 5 future technology devices international limited 47 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 appendix b - list of figures and tables list o f figures figure 2.1 ft 42 22 h block diagram ................................ ................................ ................................ . 4 figure 3.1 pin configuration v qfn - 32 (top - down view) ................................ ................................ ..... 7 figure 5.1 quadspi bus protocol when transferring in single mode ................................ ................... 16 figure 5.2 quadspi bus protocol when transferring in quad mode ................................ .................... 16 figure 5.3 sck transfer format when cpha=0 ................................ ................................ ............... 17 figure 5.4 sck transfer format when cpha=1 ................................ ................................ ............... 17 figure 5.5 spi timing ................................ ................................ ................................ .................. 18 figure 5.6 i 2 c bus protocol ................................ ................................ ................................ .......... 20 figure 5.7 i 2 c bus timing ................................ ................................ ................................ ............ 21 figure 5.8 different status when gpio3 set as gpio or interrupt input ................................ .............. 23 figure 7.1 bus powered configuration ................................ ................................ ........................... 31 figure 7.2 self powered configuration with 5v source input ................................ ............................ 32 figure 7.3 self powered configuration with 3.3v source input ................................ .......................... 33 figure 7.4 recommended ft42 2 2h crystal oscillator configuration. ................................ ................. 34 figure 7.5 usb battery charging detection ................................ ................................ .................... 35 figure 8.1 application example 1 ................................ ................................ ................................ .. 36 figure 8.2 application example 2 ................................ ................................ ................................ .. 36 figure 8.3 application example 3 ................................ ................................ ................................ .. 37 figure 8.4 application example 4 ................................ ................................ ................................ .. 37 figure 10.1 v qfn - 32 package dimensions ................................ ................................ ..................... 42 figure 10.2 v qfn - 32 package markings ................................ ................................ ......................... 43 figure 10.3 ft 42 22 h solder reflow profile ................................ ................................ ..................... 44
copyright ? 201 5 future technology devices international limited 48 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 list of tables table 3.1 FT4222H p in description ................................ ................................ ................................ .. 9 table 4.1 sck operating frequency in spi master mode ................................ ................................ .. 12 table 4.2 max. acceptable operating frequency on sck in spi slave mode ................................ ........ 12 table 5.1 FT4222H pin functions on chip configuration mode ................................ .......................... 14 table 5.2 spi timing for vccio=3.3v with 5pf ou tput pin load ................................ ........................ 18 table 5.3 spi timing for vccio= 1 . 8 v with 5pf output pin load ................................ ........................ 19 table 5.4 i 2 c timing for vccio=3.3v ................................ ................................ ............................ 22 table 6.1 absolute maximum ratings ................................ ................................ ............................ 24 table 6.2 esd and latch - up specifications ................................ ................................ .................... 24 table 6.3 operating voltage and current ................................ ................................ ....................... 25 table 6.4 i/o pin characteristics vccio = +3.3v (except usb phy pins) ................................ ........... 26 t able 6.5 i/o pin characteristics vccio = +2.5v (except usb phy pins) ................................ ........... 27 table 6.6 i/o pin characteristics vccio = +1.8v (except usb phy pins) ................................ ........... 28 table 6.7 usb phy operating voltage and current ................................ ................................ .......... 29 table 6.8 usb i/o pin (dp, dm) characteristics ................................ ................................ .............. 30 table 6.9 o tp memory characteristics ................................ ................................ ........................... 30 table 7.1 x sci input characteristics ................................ ................................ .............................. 34 table 9.1 default internal o tp memory configuration ................................ ................................ ..... 40 table 10.1 reflow profile parameter values ................................ ................................ .................... 44
copyright ? 201 5 future technology devices international limited 49 FT4222H usb2.0 to quadspi/ i2c bridge ic 1.1 document no.: ft_001011 cle arance no.: ftdi#405 appendix c - revision history document title: FT4222H usb2.0 to quadspi/ i2c bridge ic docu ment reference no.: ft_001011 clearance no.: ftdi#405 product page: http:/ /www.ftdichip.com/products/ics/FT4222H.html document feedback: send feedback revision changes date 1.0 initial release 2014 - 09 - 16 1.1 revised release 2015 - 09 - 1 0

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